شبكة التخطيط العمراني بسم الله الرحمن الرحيم
للكاتبين :
Hussein S. Mogahed1, Aziza I. Hussein 2, Ehab E. Talkhan 3, M. Moness Ali 1
1Computer & Systems Dept., Engineering College, Minia University, EGYPT.
2IEEE MemberComputer Dept. Effat College,SA
3 IEEE Member Computer & Systems Dept., Engineering College, Cairo University, EGYPT.
ABSTRACT
In this paper a new adder structure is proposed for FPGA and reconfigurable fabrications. The
proposed adder can be easily scaled to carry out many add/sub operations at a time. Hence, the
instruction level parallelism (ILP) will be increased. VHDL simulation has carried out to select
the best adder type that satisfies the area cost and delay time requirements. The simulation
results reveal that the adder which generated by the VHDL synthesis tools works more efficient
than the other types of adders. So, the proposed adder is constructed from subadders generated
by the synthesis tools. The proposed adder is partitioned to small subadders that are
interconnected using MUXs and control signals.
The proposed adder has different modes of operation depending on the operands bit width. A
small circuit has been added to the instruction decoding circuit to detect the operands bit width
and then generate the suitable control signal to select the appropriate adder operation mode.
The evaluation results reveal that the proposed adder attains higher ILP at small operands bit
width. The performance of the proposed adder has been enhanced by 212% than that of the
formal fast adder.